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커널&페이징 관련 간단히 메모 본문

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커널&페이징 관련 간단히 메모

blackcon 2015.02.11 16:54

PTE :  Page Table Entry

 - 프로세스의 페이지 정보를 담고있는 테이블이다.

 - Page 기본주소, 플래그 비트(접근비트, 현재비트, 변경비트, 읽기/쓰기 비트) 저장한다.


PAE : Physical Address Extension, 물리 주소 확장

 - 32bit환경에서는 4Gbyte이상의 메모리가 있어도 제대로 활용을 못한다.

 - 하지만 PAE기능으로 그 이상의 메모리가 사용가능하다.

 - 32bit == 2^32 == 4,294,967,296 == 4G byte

 - cr4 register가 설정됨으로써 PAE가 설정된다.



CR0

The CR0 32-bit register has 6 bits that are of interest to us. The low 5 bits of the CR0 register, and the highest bit. Here is a representation of CR0:

CR0: |PG|----RESERVED----|NE|ET|TS|EM|MP|PE|


PE
Bit 0. The Protected Environment flag. This flag puts the system into protected mode when set.
MP
Bit 1. The Monitor Coprocessor flag. This flag controls the operation of the "WAIT" instruction.
EM
Bit 2. The Emulate flag. When this flag is set, coprocessor instructions will generate an exception.
TS
Bit 3. The Task Switched flag. This flag is set automatically when the processor switches to a new task.
ET
Bit 4. The Extension Type flag. ET (also called "R") tells us which type of coprocessor is installed. If ET = 0, an 80287 is installed. if ET = 1, an 80387 is installed.
NE
Bit 5. New exceptions. If this flag is clear, FPU exceptions arrive as interrupts. If set, as exceptions.
PG
Bit 31. The Paging flag. When this flag is set, memory paging is enabled. We will talk more about that in a second.

CR2

CR2 contains a value called the Page Fault Linear Address (PFLA). When a page fault occurs, the address that access was attempted on is stored in CR2.

CR3

The upper 20 bits of CR3 are called the Page Directory Base Register (PDBR). The PDBR holds the physical address of the page directory.

CR4

CR4 contains several flags controlling advanced features of the processor.



<출처> wikipedia(http://en.wikibooks.org/wiki/X86_Assembly/Protected_Mode#CR2)




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